POST sequence of PC:
1. CPU Test
Different flags and registers within the CPU are tested. Testing is done by setting, resetting and moving the data from one register to another. If the any flag is not reset then system is halted with the execution of the halt instruction. On noticing any error system is halted.
2. BIOS ROM Test
The contents of the 8k ROM containing POST and BIOS is verified by checksum calculation method. The subroutine for ROM checksum performs EXOR addition of the content of all the locations in the 8K ROM from the start address, and if checksum result is zero, then the content of the ROM are OK. The last location contains the checksum of the previous locations and if the checksum is not zero then system is halted with the execution of the halt instruction. If BIOS is corrupted or IPL has Fault, when such errors are detected, the CPU is halted and the checkpoint 01 is present on port A pins.
3. Timer 1 Test
The timer 1 in PIT (8253) is tested. The Timer 1 is set as rate generator in mode 2 .Set an initial value in Timer 1 .Latch. Timer 1 count .After some delay read Timer1 count and check if it counts too slow. If so, the POST halts. When Timer is reset, a mild click sound is heard from the speaker on detecting an error, the CPU is halted and checkpoint 02 is present on port a pins.
4. DMA Channel 0 Test
The channel 0 of DMA controller is tested here. In this portion of POST, the channel 0 of DMA controller is initialized with appropriate start address and byte count values, so that this channel is ready for performing memory refresh DMA cycles when Timer 1 sends DMA Request signal The CPU is halted if any error is found and checkpoint 03 is present on port A pins.
5. Base 16K RAM Test
The first 16 k RAM occupying the address hex 00000 to 03FFF is tested. In each location five different test patterns (00, FF, 55, AA, 01) are written and verified by reading back. There are two types of
failures during this test:
(a) The pattern written and the pattern read are different
(b) The pattern written and the pattern read may be same but there is parity error during reading. If any error is noticed, check point 04 and failing bit pattern are alternatively outputted repeatedly on port A
pins. During warm boot, the POST skips the video RAM test.
6. CRT Controller Test
CRT controller 6845 and the video buffer RAM in the display adapter are tested. Display adapters can be configured by setting the DIP switches which post identifies by reading DIP switch If no display
adapter is present, the POST skips all video adapter tests If any error is noticed, beep sounds are produced on the speaker.
7. Motherboard Support Chips Test
The interrupt controller, timer (8253) and keyboard interface are tested here. If any error is noticed, an error code is displayed on the CRT monitor.
8. RAM Test
RAM after the first 16 kb is tested here for five different patterns (AA, 55, FF, 01 and 00). A detailed error message indicating the failing address and failing bits is displayed on the CRT screen.
9. Optional ROM Test
The ROMs in hard disk controller are tested by checksum method.
10. Peripheral Controller Test
The Floppy Controller, Parallel Ports, Serial Ports and Hard Disk Controller are tested here. A detailed error message is displayed on the screen if any error is noticed. At the end of all the tests, the POST
passes control to the boot strap loader program in BIOS. The boot strap loader reads the initial program from track 0 on floppy disk or hard disk. This initial program reads more programs from the floppy
disk or hard disk, which is nothing but the DOS.
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